Semiconductor integrated circuits (ICs) have evolved towards increased density and device shrinkage. One important structure in the manufacture of ICs is isolation structures. Devices formed in the silicon substrate must be isolated from one another. Establishing effective isolation in submicron ICs in the face of decreased isolation space is a complicated and challenging task.
One conventional method for isolation involves oxidizing a bare silicon wafer in a furnace to grow a pad oxide layer of about 100 to 250 angstroms thickness. The pad oxide layer is most typically formed from silicon dioxide. A furnace nitride layer of about 1500 to 2000 angstroms thickness is then deposited on the pad oxide layer. A masking and etching step is then performed to form trenches about 0.4 to 0.5 .mu.m in depth. A thermal oxide liner of about 150 to 300 angstroms is then grown along the etched trench sidewall and on the surface of the nitride layer. Next, oxide is then deposited in the trenches by chemical vapor deposition (CVD). The CVD oxide is then planarized by a chemical mechanical polishing (CMP).
Planarization by the CMP presents several problems. The removal rate of the CVD oxide by the CMP is higher than the removal rate of the nitride, causing dishing in wide trenches. This dishing effect degrades the planarity of a layer, and it also impacts the yield of the device. Furthermore, endpoint detection is not accurate during the CMP because the ratio of the removal rate of the CVD oxide to the removal rate of the nitride is about 3 or 4 to 1. Increasing this ratio to improve endpoint detection would result in increased dishing under this conventional method. Therefore, a need arises for a simple and efficient method of forming a trench isolation that reduces dishing, while at the same time making endpoint detection available during the CMP.